In order to produce improvements to logic circuits, it is desirable to produce device structures, particularly field-effect transistors (FETs), that work at higher frequencies and lower powers. The standard architecture for digital circuit design is CMOS. To achieve CMOS circuits, both n-FETs (with electrons as charge carriers) and p-FETs (with holes as charge carriers) are required.
Conventional CMOS design is largely based on Si semiconductor technology. For n-FETs, very high operational frequencies and low operating powers have been achieved using InSb as a semiconductor. In this system, a layer of AlxIn1-xSb is grown on a suitable substrate, such as GaAs, and a thin device layer of InSb grown over this. A donor layer to provide electrons is grown over the device layer, separated from it by a small AlxIn1-xSb spacer layer. The device layer is capped by a suitable layer, again AlxIn1-xSb to confine the charge carriers in the device layer region, which forms a quantum well. For regions with a composition of AlxIn1-xSb, the value of x may vary from region to region. InSb has a very high electron mobility, and extremely good results have been achieved—n-FETs with a 350 GHz operating speed and an operating voltage of 0.5 V have been produced.
Strained InSb quantum well structures are also suitable for use in p-FETs. There is a lattice mismatch between the InSb and the AlxIn1-xSb which leads to compressive strain in the quantum well and hence good hole mobility. p-FETs with transconductance and cut-off frequency significantly higher than conventional Si or other III-V semiconductor systems have been achieved. Nonetheless, the performance achievable with p-type strained InSb quantum well field effect transistors (QWFETs) does not compare with that achievable for n-type QWFETs.
Other systems have also been investigated to produce high speed p-channel devices suitable for use in CMOS logic—these systems include SiGe, Ge, InGaSb and carbon nanotubes. None of these system currently provides a route to producing p-FETs with performance comparable to that of n-type indium antimonide QWFETs.
It is therefore desirable to produce a device structure with p-channel properties that allow it to be used in a p-FET with low power and high frequency performance comparable to, and compatible with, that achievable with n-type InSb QWFETs. This would allow formation of high performance p-type and n-type QWFETs to be grown on a common substrate, allowing CMOS logic to be realised with low power consumption.